Flash memory has become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks.
Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding charges and is separated from source and drain regions contained in a substrate by a layer of thin oxide. Each of the memory cells can be electrically charged by injecting electrons from the drain region through the oxide layer onto the floating gate. The charges can be removed from the floating gate by tunneling the electrons to the source through the oxide layer during an erase operation. The data in a memory cell is thus determined by the presence or absence of a charge on the floating gate.
Flash cells come in two major types: stack gate flash cells and split gate flash cells. FIG. 1 illustrates a tri-gate split gate flash cell 2, which includes a floating gate 12, a control gate 14, and a selection gate 16. Selection gate 16 is typically referred to as wordline 16, as it is commonly connected to a wordline of the memory array. The split gate flash cells exhibit an improved performance over the stacked gate flash cells. Particularly, with the access control provided by the wordline 16, over-erase can be prevented.
Flash memory cells are typically formed along with other circuits (non-memory circuits), such as core circuits. An exemplary MOS device 18 in non-memory circuits is also shown in FIG. 1. Since flash memory cells typically have more layers, the height of the flash memory cells are typically greater than the height of non-memory MOS devices, and thus a topography height difference TH appears. For great-scale integrated circuit formation technologies, such as 130 nm and higher, the topography height difference can be overcome, although process-difficulty still occurs. For small-scale integrated circuit formation technologies, such as 90 nm and lower, the topography height difference is hard to overcome. This problem can be explained using 45 nm technology as an example. At this scale, the topography height difference TH may be as high as 2000 Å. The depth of focus, which indicates how deep the imaging light used by lithography instruments can effectively penetrate into the photo resist, is about 1800 Å. Therefore, any process variation may cause under-exposure of the photo resist.
In addition, with the uneven wafer surface caused by the topography height difference, it is hard for a lithography instrument to measure and be aligned to the surface of the wafer.
To solve the above-discussed problems, new flash memory cell structures and/or new formation methods for forming the flash memory cell structures are needed.